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Eight Character 5.0 mm (0.2 inch) Glass/Ceramic Intelligent 5 x 7 Alphanumeric Displays for Military Applications Technical Data
HDSP-2131 HDSP-2132 HDSP-2133 HDSP-2179
Features
* Wide Operating Temperature Range -55C to +85C * Smart Alphanumeric Display On-Board CMOS IC Built-In RAM ASCII Decoder LED Drive Circuitry * 128 ASCII Character Set * 16 User Definable Characters * Programmable Features Individual Character Flashing Full Display Blinking Multi-Level Dimming and Blanking Self Test Clear Function * Read/Write Capability * Full TTL Compatibility * HDSP-2131/-2133/-2179 Useable in Night Vision Lighting Applications * Categorized for Luminous
Intensity * HDSP-2131/2133 Categorized for Color * Excellent ESD Protection * Wave Solderable * X-Y Stackable
Description
The HDSP-2131 (yellow), HDSP2179 (orange), HDSP-2132 (high efficiency red) and the HDSP2133 (green) are eight-digit, 5 x 7 dot matrix, alphanumeric displays. The 5.0 mm (0.2 inch) high characters are packaged in a standard 7.64 mm (0.30 inch) 32 pin DIP. The on-board CMOS IC has the ability to decode 128 ASCII characters, which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in an onboard RAM. Seven brightness levels provide versatility in
adjusting the display intensity and power consumption. The HDSP213X is designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional eight-bit data bus. These features make the HDSP213X ideally suited for applications where a hermetic, low power alphanumeric display is required.
Devices
Yellow HDSP-2131 High Efficiency Red HDSP-2132 High Performance Green HDSP-2133 Orange HDSP-2179
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Package Dimensions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FUNCTION CLS CLK WR CE RST RD NO PIN NO PIN NO PIN NO PIN D0 D1 D2 D3 NC VDD
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FUNCTION GND (SUPPLY) GND (LOGIC) D4 D5 D6 D7 NO PIN NO PIN NO PIN NO PIN FL A0 A1 A2 A3 A4
HDSP-213X/2179 Note: 1. All dimensions are in mm (inches). 2. Unless otherwse specified tolerance is 0.30 mm (0.015). 3. For green and yellow devices only. 4. Leads are copper alloy, solder dipped.
Absolute Maximum Ratings Supply Voltage, VDD to Ground[1] ........................................ -0.3 to 7.0 V Operating Voltage, VDD to Ground[2] ............................................. 5.5 V Input Voltage, Any Pin to Ground .............................. -0.3 to VDD +0.3 V Free Air Operating Temperature Range, TA .................... -55C to +85C Storage Temperature, TS .............................................. -55C to +100C CMOS IC Junction Temperature, TJ (IC) .................................... +150C Wave Solder Temperature, 1.59 mm (0.063 in.) below Body ............................... 250C for 3 secs ESD Protection @ 1.5 k, 100 pF ......................... VZ = 4 kV (each pin)
Notes: 1. Maximum voltage is with no LEDs illuminated. 2. 20 dots ON in all locations at full brightness.
ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED WITH THE HDSP-2131, HDSP-2132, HDSP-2133, AND HDSP-2179.
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Character Set
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Recommended Operating Conditions
Parameter Supply Voltage Symbol VDD Minimum 4.5 Nominal 5.0 Maximum 5.5 Units V
Electrical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 V (unless otherwise specified) Parameter Input Leakage (Input without pullup) Input Current (Input with pullup) IDD Blank IDD 8 digits 12 dots/character[3] IDD 8 digits 20 dots/character[3] Input Voltage High Input Voltage Low Output Voltage High Symbol II Min. -10.0 25C 25C Typ.[1] Max.[1] Max.[2] Units +10.0 A Test Conditions VIN = 0 to VDD, pins CLK, D0-D7, A0-A4 VIN = 0 to VDD, pins RST, CLS, WR, RD, CE, FL VIN = VDD "V" on in all 8 locations "#" on in all 8 locations VDD = 5.5 V VDD = 4.5 V VDD = 4.5 V, IOH = -40 A VDD = 4.5 V, IOL = 1.6 mA VDD = 4.5 V, IOL = 40 A
IIP
-30.0
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18
30
A
IDD (BLK) IDD(V) IDD(#) VIH VIL VOH VOL 2.0 GND -0.3 V 2.4
0.5 200 300
1.5 255 370
2.0 330 430 VDD +0.3 0.8
mA mA mA V V V
Output Voltage Low D0-D7 Output Voltage Low CLK Thermal Resistance IC Junction-to-PIN
0.4 0.4
V V C/W
RJ-PIN
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Notes: 1. VDD = 5.0 V. 2. Maximum IDD occurs at -55C. 3. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x Average IDD (#).
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Optical Characteristics at 25C[4]
VDD = 5.0 V at Full Brightness High Efficiency Red HDSP-2132 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV PEAK d Minimum 2.5 Typical 7.5 635 626 Units mcd nm nm
Orange HDSP-2179 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV PEAK d Minimum 2.5 Typical 7.5 600 602 Units mcd nm nm
Yellow HDSP-2131 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV PEAK d Minimum 2.5 Typical 7.5 583 585 Units mcd nm nm
High Performance Green HDSP-2133 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol IV PEAK d Minimum 2.5 Typical 7.5 568 574 Units mcd nm nm
Note: 4. Refers to the initial case temperature of the device immediately prior to the light measurement.
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AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specified. Reference Number 1
Symbol tACC
Description Display Access Time Write Read Address Setup Time to Chip Enable Chip Enable Active Time[2, 3] Write Read Address Hold Time to Chip Enable Chip Enable Recovery Time Chip Enable Active Prior to Rising Edge of [1,2] Write Read Chip Enable Hold Time to Rising Edge of Read/Write Signal[2, 3] Write Active Time [2,3] Data Valid Prior to Rising Edge of Write Signal Data Write Hold Time Chip Enable Active Prior to Valid Data Read Active Prior to Valid Data Read Data Float Delay Reset Active Time[4]
Min.[1]
Units
210 230 10
ns ns
2 3
tACS tCE
140 160 20 60
ns ns ns
4 5 6
tACH tCER tCES
140 160
ns
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tCEH tW tWD tDH tR tRD tDF tRC
0 100 50 20 160 75 10 300
ns ns ns ns ns ns ns ns
8 9 10 11 12 13
Notes: 1. Worst case values occur at an IC junction temperature of 150C. 2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4. The display must not be accessed until after 3 clock pulses (110 s min. using the internal refresh clock) after the rising edge of the reset line.
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AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specified. Symbol FOSC FRF[5] FFL[6] tST[7]
Notes: 5.FRF = FOSC /224. 6.FFL = FOSC /28,672. 7.tST = 262,144/FOSC.
Description Oscillator Frequency Display Refresh Rate Character Flash Rate Self Test Cycle Time
25C Typical 57 256 2 4.6
Minimum[1] 28 128 1 9.2
Units kHz Hz Hz Sec
Write Cycle Timing Diagram
INPUT PULSE LEVELS WITH 0.6 V TO 2.4 V INPUT PULSE LEVELS: 0.6 V TO 2.4 V
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Read Cycle Timing Diagram
Character Font
Relative Luminous Intensity vs. Temperature
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Electrical Description
Pin Function RESET (RST, pin 5) FLASH (FL, pin 27) Reset initializes the display. FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. Each location in memory has a distinct address. Address inputs (A0-A2) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User-Defined Character) RAM. A3-A4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory FL 0 1 1 1 1 CLOCK SELECT (CLS, pin 1) CLOCK INPUT/OUTPUT (CLK, pin 2) WRITE (WR, pin 3) CHIP ENABLE (CE, pin 4) READ (RD, pin 6) DATA Bus (D0-D7, pins 11-14, 19-22) GND(SUPPLY) (pin 17) GND(LOGIC) (pin 18) VDD(POWER) (pin 16) A4 X 0 0 1 1 A3 X 0 1 0 1 Section of Memory Flash RAM UDC Address Register UDC RAM Control Word Register Character RAM A2 A1 A0
ADDRESS INPUTS (A0-A4, pins 28-32)
Character Address Don't Care Row Address Don't Care Character Address
This input is used to select either an internal (CLS = 1) or external (CLS = 0) clock source. Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. Data is written into the display when the WR input is low and the CE input is low. This input must be at a logic low to read or write data to the display and must go high between each read and write cycle. Data is read from the display when the RD input is low and the CE input is low. The Data bus is used to read from or write to the display. This is the analog ground for the LED drivers. This is the digital ground for internal logic. This is the positive power supply input.
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Figure 1. HDSP-213X/-2179 Internal Block Diagram.
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Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP-213X/-2179 display. The CMOS IC consists of an 8 byte Character RAM, an 8 bit
Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register, and the refresh circuitry necessary to synchronize the decoding and
driving of eight 5 x 7 dot matrix characters. The major user accessible portions of the display are listed below:
Character RAM Flash RAM User-Defined Character RAM (UDC RAM) User-defined Character Address Register (UDC Address Register) Control Word Register
This RAM stores either ASCII character data or a UDC RAM address. This is a 1 x 8 RAM which stores Flash data. This RAM stores the dot pattern for custom characters. This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. This register allows the user to adjust the display brightness, flash individual characters, blink, self test or clear the display.
Character Ram Figure 2 shows the logic levels needed to access the HDSP-213X Character RAM. During a normal access the CE = "0" and either RD = "0" or WR = "0". However, erroneous data may be written into the Character RAM if the Address lines are unstable when CE = "0" regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between an ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0-D6 are used to input ASCII data and D0-D3 are used to input a UDC address.
Figure 2. Logic Levels to Access the Character RAM.
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UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0-D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character requires eight write cycles. One cycle is used to store the UDC RAM address in the UDC Address Register. Seven cycles are used to store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an "F." A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM. Address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attribute. D0 is used to store or remove the flash attribute. D0 = "1" stores the attribute and D0 = "0" removes the attribute.
Figure 3. Logic Levels to Access a UDC Character.
Figure 4. Data to Load "F" into the UDC RAM.
When the attribute is enabled through bit 3 of the Control Word and a "1" is stored in the Flash RAM, the corresponding character will flash at approximately 2 Hz.
The actual rate is dependent on the clock frequency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672.
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Figure 5. Logic Levels to Access the Flash RAM.
Control Word Register
Figure 6 shows how to access the Control Word Register. This is an eight bit register which performs five functions. They are Brightness control, Flash RAM control, Blinking, Self Test and Clear. Each function is independent of the others. However, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent bright-ness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a "1," the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a "1," the associated digit will flash at
Figure 6. Logic Levels to Access the Control Word Register
Table 2. Current Requirements at Different Brightness Levels Symbol IDD (V) D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 % Brightness 100 80 53 40 27 20 13 25C Typical 200 160 106 80 54 40 26 Units mA mA mA mA mA mA mA
approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display systems see the Reset section. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all
eight digits of the display. When this bit is a "1" all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see the Reset section.
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Self Test Function (Bits 5, 6) Bit 6 of the Control Word Register is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test and bit 5 = "0" indicates a failed self test. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal routines which exercises major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to "1." The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test function, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address Register is set to all ones.
Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a "1" will start the clear function. Three clock cycles (110 s min. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a "0." The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "0"s. The UDC RAM, UDC Address Register, and the remainder of the Control Word are unaffected.
are unaffected. All displays which operate with the same clock source must be simultaneously reset to synchronize the Flashing and Blinking functions.
Mechanical and Electrical Considerations
The HDSP-213X/-2179 is a 32 pin dual-in-line package with 24 external pins, which can be stacked horizontally and vertically to create arrays of any size. The HDSP-213X/-2179 is designed to operate continuously from -55C to +85C with a maximum of 20 dots ON per character. Illuminating all thirty-five dots at full brightness is not recommended. The HDSP-213X/-2179 is assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a ceramic substrate. A glass window is placed over the ceramic substrate creating an air gap over the LED wire bonds. A second glass window creates an air gap over the CMOS IC. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering and visual inspection of the IC.
Display Reset
Figure 7 shows the logic levels needed to Reset the display. The display should be Reset on Powerup. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 s min. using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all "0"s. The UDC RAM and UDC Address Register
Figure 7. Logic Levels to Reset the Display.
Figure 8. Maximum Power Dissipation vs. Ambient Temperature Derating Based on TJMAX = 125C.
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The inputs to the CMOS IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be used. Prior to use, the HDSP-213X should be stored in antistatic packages or conductive material. During assembly, a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static charge buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VDD (VIN > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Transient input voltages should be eliminated.
TJ(IC) MAX = TA + (PDMAX) (RJ-PIN + RPIN-A) Where PDMAX = (VDDMAX) (IDDMAX) IDDMAX = 370 mA with 20 dots ON in eight character locations at 25C ambient. This value is from the Electrical Characteristics table. PDMAX = (5.5 V) (0.370 A) = 2.04 W
ESD Susceptibility
These displays have ESD susceptibility ratings of CLASS 3 per DOD-STD-1686 and CLASS B per MIL-STD-883C.
Soldering and Post Solder Cleaning Instructions for the HDSP-213X/-2179
The HDSP-213X/-2179 may be hand soldered or wave soldered with SN63 solder. When hand soldering it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C 5C (473F 9F), and dwell in the wave should be set between 11/2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 105C (221F) as measured on the solder side of the PC board. For further information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components.
Ground Connections
Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnects between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltage below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch.
Thermal Considerations
The HDSP-213X/-2179 has been designed to provide a low thermal resistance path from the CMOS IC to the 24 package pins. This heat is then typically conducted through the traces of the user's printed circuit board to free air. For most applications no additional heatsinking is required. The maximum operating IC junction temperature is 150C. The maximum IC junction temperature can be calculated using the following equation:
Contrast Enhancement
When used with the proper contrast enhancement filters, the HCMS-213X/-2179 series displays are readable daylight ambients. Refer to Application Note 1029 Luminous Contrast and Sunlight Readability of the HDSP235X Series Alphanumeric Displays for Military Applications for information on contrast enhancement for daylight
ambients. Refer to Application Note 1015 Contrast Enhancement Techniques for LED Displays for information on contrast enhancement in moderate ambients.
Night Vision Lighting
When used with the proper NVG/ DV filters, the HDSP-2131, HDSP-2179 and HDSP-2133 may be used in night
vision lighting applications. The HDSP-2131 (yellow), HDSP-2179 (orange) displays are used as master caution and warning indicators. The HDSP-2133 (high performance green) displays are used for general instrumentation. For a list of NVG/DV filters and a discussion on night vision lighting technology, refer to Application Note 1030 LED Displays and Indicators and Night Vision
Imaging System Lighting. An external dimming circuit must be used to dim these displays to night vision lighting levels to meet NVIS radiance requirements. Refer to AN 1039 Dimming HDSP-213X Displays to Meet Night Vision Lighting Levels.
Intensity Bin Limits
Bin G H I J K Intensity Range (mcd) Min. Max. 2.50 4.00 3.41 6.01 5.12 9.01 7.68 13.52 11.52 20.28
Note: Test conditions as specified in Optical Characteristic table.
Color Bin Limits
Color Green Bin 1 2 3 4 3 4 5 6 Color Range (nm) Min. Max. 576.0 580.0 573.0 577.0 570.0 574.0 567.0 571.5 581.5 585.0 584.0 587.5 586.5 590.0 589.0 592.5
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For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. Obsoletes 5988-2258EN July 19, 2004 5988-4667EN
Yellow
Note: Test conditions as specified in Optical Characteristic table.

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